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CDB42406

Evaluation Board For CS42406

Cirrus Logic 

CDB42406

1.7.3f Setup 12

A DSP connected to DSP I/O HDR masters all clocks for the DAC and provides data to

the DAC. Using a DSP connected to DSP I/O HDR, the CS42406 ADC masters its sub-

clocks and are output onto DSP_ADC_LRCK and DSP_ADC_SCLK. The subclocks for

the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent

control of the sample rate for the ADC and DAC. For implementation of this setup option,

set DIP switch S4 (SW[3:0]) to ‘1100’b.

AUDIO

MCLK

CS8416

RMCK

OM CK

OLRCK/

O SCLK

SDOUT

CS8406

OMCK

ILR C K /

ISCLK

SDIN

CS42406

M CLK

DAC_LRCK /

DAC_SCLK

DAC_SDINx

A D C _L R C K /

A D C _S C L K

ADC_S DOUT

DSP I/O

HDR

DSP_MCLK

D S P _ D A C _ LR C K /

DSP_DA C_SCLK

DS P_S DINx

D S P _ A D C _ LR C K /

D S P _ A D C _S C L K

DSP_SDOUT

Figure 13. DSP Routing - Setup 12

1.7.4 No Routing

The remaining setup options will tri-state all clock/data output on the CPLD with the ex-

ception of the ADC_SDOUT from the CS42406 to the inputs of the CS8406 and

DSP_I/O_HDR.

AUDIO

MCLK

CS8416

RMCK

OMCK

OLRCK/

OSCLK

SD OUT

CS8406

OMCK

ILRCK/

ISCLK

SDIN

CS42406

MCLK

DAC_LRCK/

DAC_SCLK

DAC_SDINx

ADC_LRCK/

ADC_SC LK

ADC_SDOUT

DSP I/O

HDR

DSP_M CLK

DS P_DAC_LRCK/

DSP _D AC_SCLK

DS P_SDINx

DS P_ADC_LRCK/

DSP _A DC_SCLK

DSP_SD OU T

Figure 14. No Routing

14

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