CDB4265(2005) Ver la hoja de datos (PDF) - Cirrus Logic

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CDB4265
(Rev.:2005)

Evaluation Board for CS4265

Cirrus Logic 

CDB4265

2. SYSTEM CLOCKS AND DATA

The CDB4265 implements comprehensive clock and data routing capabilities. Configuration of the clock and data

routing can be easily achieved using the controls within the Board Controls group box on the CDB4265 Controls tab

in the GUI software application.

2.1 Clock Routing

The master clock signal (MCLK) may be sourced from the canned oscillator (Y1), the CS8416 S/PDIF re-

ceiver, or the PCM I/O header (J15)

The sub-clock signals (SCLK and LRCK) may be sourced from the CS4265 in master mode, the CS8416 in

master mode, or the PCM I/O header.

Clock routing configuration is achieved using the MCLK Source and Subclock Source controls within the

Board Controls group box on the CDB4265 Controls tab in the GUI software application.

2.2 Data Routing

The CDB4265 implements comprehensive data routing capabilities. The SDIN source of the CS4265 may

be easily selected using the provided GUI software application.

2.2.1 CS4265 SDIN1 and SDIN2 Source

The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may

source the serial data input of the CS4265. Configuration of the CS4265 SDIN1 and SDIN2 source is

achieved using the respective CS4265 SDIN Source control within the Board Controls group box on the

CDB4265 Controls tab in the GUI software application.

2.2.2 CS4265 TXSDIN Source

The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may

source the serial data input of the CS4265. Configuration of the CS4265 TXSDIN source is achieved using

the CS4265 TxSDIN Source control within the S/PDIF Transmitter group box on the CDB4265 Controls tab

in the GUI software application.

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DS657DB1

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