CRD42L51(2005) Ver la hoja de datos (PDF) - Cirrus Logic

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fabricante

CRD42L51
(Rev.:2005)

Low Power, Stereo CODEC with Headphone Amp

Cirrus Logic 

CS42L51

LRCK

SCLK

SDOUT

SDIN

ts(LK-SK)

td(MSB)

ts(SD-SK)

//

//

tP

//

//

th(SK-SDO)

//

MSB

//

th

//

MSB

//

ts(SDO-SK)

MSB-1

MSB-1

Figure 4. Serial Audio Interface Slave Mode Timing

Master Mode (Note 17)

Output Sample Rate (LRCK)

Parameters

LRCK Duty Cycle

SCLK Frequency

SCLK Duty Cycle

SCLK Rising Edge to SDOUT Output Delay

LRCK Edge to SDOUT MSB Output Delay

SDOUT Setup Time Before SCLK Rising Edge

SDOUT Hold Time After SCLK Rising Edge

SDIN Setup Time Before SCLK Rising Edge

SDIN Hold Time After SCLK Rising Edge

Symbol Min

All Speed Modes Fs

-

45

1/tP

-

45

td

-

td(MSB)

-

ts(SDO-SK)

30

th(SK-SDO)

30

ts(SD-SK)

20

th

20

Max Units

M------C-----L---K---

Hz

128

55

%

64•Fs

Hz

55

%

--------1---------

s

MCLK

40

ns

-

ns

-

ns

-

ns

-

ns

Notes:

15. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are set-

tled.

16. See “Example System Clock Frequencies” on page 75 for typical MCLK frequencies.

17. See “Master” on page 38.

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(SD-SK)

//

//

tP

//

//

th(SK-SDO)

//

MSB

//

th

//

MSB

//

ts(SDO-SK)

MSB-1

MSB-1

Figure 6. Serial Audio Interface Master Mode Timing

DS679A2

21

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