CS42L51-DNZ Ver la hoja de datos (PDF) - Cirrus Logic
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CS42L51-DNZ Datasheet PDF : 88 Pages
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CS42L51
Master Mode (Note 17)
Parameters
Symbol Min
Max Units
Output Sample Rate (LRCK)
All Speed Modes
(Note 17)
Fs
-
M------C-----L---K---
Hz
128
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
45
1/tP
-
45
td(MSB)
-
ts(SDO-SK)
20
th(SK-SDO)
30
ts(SD-SK)
20
th
20
55
%
64•Fs
Hz
55
%
52
ns
-
ns
-
ns
-
ns
-
ns
14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies.
16. See
17. “Master” on page 39
18. “MCLK” refers to the external master clock applied.
LRCK
SCLK
SDOUT
SDIN
ts(LK-SK)
td(MSB)
ts(SD-SK)
//
//
tP
//
//
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
LRCK
SCLK
SDOUT
SDIN
td(MSB)
ts(SD-SK)
//
//
tP
//
//
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 5. Serial Audio Interface Master Mode Timing
DS679F1
21
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