CDB4338 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4338 Datasheet PDF : 14 Pages
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CDB4334/8/9
ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters and a pair of 3-pole active filters.
The passive filters are provided as an example for
cost-sensitive desigins. The active filters demon-
strate a higher performance alternative with better
out-of-band noise rejection. The passive filters,
Fig. 4, have a corner frequency of approximately
95 kHz with JP3 and JP6 installed and 190 kHz
without JP3 and JP6. The 3-pole active filters are
shown in Fig. 3. The output filter options are se-
lected via the Left and Right Channel filter jump-
ers, Fig. 2.
INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 10. The 74HC243 transceiver functions as
an I/O buffer where jumpers HDR1-HDR6 deter-
mine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a re-
ceiver with jumpers HDR1-HDR6 in the EXTER-
NAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4334/8/9 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 9 shows CDB power arrange-
ments. The CDB4334/8/9 ground plane is divided
in a manner to control to digital return currents in
order to minimize noise. The decoupling capacitors
are located as close to the CS4334/8/9 as possible.
Extensive use of ground plane fill on both the ana-
log and digital sections of the evaluation board
yield large reductions in radiated noise effects.
DS248DB2
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