CDB4351(2004) Ver la hoja de datos (PDF) - Cirrus Logic

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CDB4351
(Rev.:2004)

192 kHz Stereo DAC with 2 Vrms Line Out

Cirrus Logic 

CS4351

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF)

Parameter

Symbol

Min

Max

CCLK Clock Frequency

fsclk

-

6

RST Rising Edge to CS Falling

tsrs

500

-

CCLK Edge to CS Falling

(Note 8)

tspi

500

-

CS High Time Between Transmissions

tcsh

1.0

-

CS Falling to CCLK Edge

tcss

20

-

CCLK Low Time

tscl

66

-

CCLK High Time

tsch

66

-

CDIN to CCLK Rising Setup Time

tdsu

40

-

CCLK Rising to DATA Hold Time

(Note 9)

tdh

15

-

Rise Time of CCLK and CDIN

(Note 10)

tr2

-

100

Fall Time of CCLK and CDIN

(Note 10)

tf2

-

100

Unit

MHz

ns

ns

µs

ns

ns

ns

ns

ns

ns

ns

Notes: 8. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

9. Data must be held for sufficient time to bridge the transition time of CCLK.

10. For FSCK < 1 MHz.

RST

t srs

CS

CCLK

C D IN

t spi t css

t scl t sch

t csh

t r2

t f2

t dsu t dh

Figure 3. Control Port Timing - SPI Format (Write)

DS566PP2

13

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