CS4351 Ver la hoja de datos (PDF) - Cirrus Logic

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CS4351

192 kHz Stereo DAC with 2 Vrms Line Out

Cirrus Logic 

Switching Characteristics - Control Port - I²C® Format

(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF)

Parameter

Symbol

Min

SCL Clock Frequency

fscl

-

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 7)

thdd

0

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trc

-

Fall Time SCL and SDA

tfc, tfc

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

tack

300

Notes:

7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

CS4351

Max

100

-

-

-

-

-

-

-

-

1

300

-

1000

Unit

kHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

ns

RST

t irs

Stop

Start

SDA

t buf

t hdst

t high

Repeated

S ta rt t rd

t hdst

Stop

t fd

t fc

t susp

SCL

t

low

t

hdd

t sud t ack

t sust

t rc

Figure 2. Control Port Timing - I²C Format

DS566F1

11

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