CS4361-CZZ(2005) Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Lista de partido
CS4361-CZZ Datasheet PDF : 23 Pages
| |||
CS4361
4.3 De-Emphasis
The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive falling edges of
LRCK. This function is available only in the internal serial clock mode when LRCK < 50 kHz.
Gain
dB
0dB
-10dB
T1=50 µs
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
4.4 Mode Select
Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after RST
is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in table 3.
.
Mode pin is:
Tied to VL
Tied to GND
Tied to LRCK
Tied to MCLK
Mode
I2S
Left Justified
Right Justified - 24 bit
Right Justified - 16bit
Figure
7
8
9
10
Table 3. Mode pin settings
4.5 Initialization and Power-Down
The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the power-down
state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage
reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are powered down. The de-
vice will remain in the power-down mode until RST is released and MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency
ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and
switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
DS672A2
15
Share Link: 