CDB4362(2004) Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4362 Datasheet PDF : 42 Pages
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CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(For KQZ TA = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 19)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 20)
fscl
tirs
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
trc, trc
tfc, tfc
tsusp
tack
-
100
kHz
500
-
ns
4.7
-
µs
4.0
-
µs
4.7
-
µs
4.0
-
µs
4.7
-
µs
0
-
µs
250
-
ns
-
1
µs
-
300
ns
4.7
-
µs
-
(Note 21)
ns
Notes: 19.
20.
21.
Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2----5--6--1---×5-----F---s- for Single-Speed Mode, 1---2---8--1---×5-----F---s- for Double-Speed Mode, 6---4----1-×--5---F---s- for Quad-Speed Mode.
RST
t irs
Stop
S ta rt
SDA
SCL
t buf
t hdst
t
lo w
t high
thdd
t sud
tack
R epe ate d
S ta rt
t rd
t hdst
Stop
t fd
t fc
t susp
t sust
t rc
Figure 3. Control Port Timing - I2C Format
10
DS257F1
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