CS4364-CQZ Ver la hoja de datos (PDF) - Cirrus Logic
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CS4364-CQZ Datasheet PDF : 50 Pages
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CS4364
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 18)
(Note 19)
(Note 20)
(Note 20)
Symbol
fsclk
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
Min
-
500
500
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes:
18. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For FSCK < 1 MHz.
RST
t srs
CS
CCLK
CDIN
t spi t css
t scl t sch
t r2
t f2
t dsu t dh
Figure 6. Control Port Timing - SPI Format
t csh
DS619A1
17
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