CS4385
LRCK
SCLK
SDINx 1 0
Left Channel
Right Channel
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 13. Format 4 - Right Justified 20-bit Data
LRCK
SCLK
SDINx 1 0
Left Channel
Right Channel
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 14. Format 5 - Right Justified 18-bit Data
3.3.1 OLM #1
OLM #1 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on
SDIN1. The last two channels are input on SDIN4.
LRCK
64 clks
Left Channel
64 clks
Right Channel
SCLK
SDIN1
MSB
LSB MSB
LSB MSB
LSB
DAC_A1
DAC_A2
DAC_A3
20 clks
20 clks
20 clks
MSB
LSB MSB
LSB MSB
LSB
DAC_B1
DAC_B2
DAC_B3
20 clks
20 clks
20 clks
MSB
SDIN4
DAC_A4
20 clks
DAC_B4
20 clks
Figure 15. Format 8 - One Line Mode 1
DS671A1
21