CS5364-CQZ Ver la hoja de datos (PDF) - Cirrus Logic
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CS5364-CQZ Datasheet PDF : 42 Pages
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SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF
Parameter
Symbol
Min
Max
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
600
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 1)
thdd
0
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
tsud
600
trc
-
tfc
-
tsusp
4.7
tack
300
100
-
1
300
-
1000
Notes:
1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
CS5364
Unit
kHz
ns
µs
µs
ns
µs
ns
µs
ns
RST
t irs
Stop
Start
SDA
t buf
t hdst
t high
S CL
t
lo w
t
hdd
t sud t ack
Figure 5. I²C Timing
Repe ated
Sta rt t rd
t hdst
Stop
t fd
t fc
t susp
t sust
t rc
DS625F4
17
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