CL-PS7111
Low-Power System-on-a-Chip
2.2.2
Numeric Pin Listing (cont.)
Pin
No.
Signal
Buffer
Reset and
Pin Test
Reset State
Pin
No.
167
VDD
Pad power
–
189
168
VSS
Pad power
–
190
169
A[4]
I/O - strength 1
Low
191
170
D[4]
I/O - strength 1
Low
192
171
A[3]
I/O - strength 2
Low
193
172
D[3]
I/O - strength 1
Low
194
173
A[2]
I/O - strength 2
Low
195
174
VSS
–
196
175
D[2]
I/O - strength 1
Low
197
176
A[1]
I/O - strength 1
Low
198
177
D[1]
I/O - strength 1
Low
199
178
A[0]
I/O - strength 1
Low
200
179
D[0]
I/O - strength 1
Low
201
180
VSS
Core power
–
202
181
VDD
Core power
–
203
182
VSS
Pad power
–
204
183
VDD
Pad power
–
205
184
CL[2]
I/O - strength 1
Low
206
185
CL[1]
I/O - strength 1
Low
207
186
FRM
I/O - strength 1
Low
208
a Pins that are ‘no connect’ (N/C) may have a signal.
b Also has analog bypass path for oscillator test.
Signal
DD[2]
VSS
DD[1]
DD[0]
NRAS[1]
NRAS[0]
NCAS[3]
NCAS[2]
VDD
VSS
NCAS[1]
NCAS[0]
NMWE
NMOE
VSS
NCS[0]
NCS[1]
NCS[2]
NCS[3]
NCS[4]
Buffer
Reset and
Pin Test
Reset State
I/O - strength 1
Low
–
I/O - strength 1
I/O - strength 1
I/O - strength 1
I/O - strength 1
Low
Low
High
High
I/O - strength 1
I/O - strength 1
Pad power
Pad power
I/O - strength 2
High
High
–
–
High
I/O - strength 2
I/O - strength 1
I/O - strength 1
High
High
High
–
I/O - strength 1
I/O - strength 1
I/O - strength 1
I/O - strength 1
I/O - strength 1
High
High
High
High
Low
September 1997
PRELIMINARY DATA BOOK v2.0
15
PIN INFORMATION