CDK-2000-CLK(2008) Ver la hoja de datos (PDF) - Cirrus Logic

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CDK-2000-CLK
(Rev.:2008)

Fractional-N Clock Multiplier

Cirrus Logic 

1. PIN DESCRIPTION

CS2100-OTP

VD

1

GND

2

CLK_OUT

3

AUX_OUT

4

CLK_IN

5

10

M0

9

M1

8

M2

7

XTI/REF_CLK

6

XTO

Pin Name

VD

GND

CLK_OUT

AUX_OUT

CLK_IN

XTO

XTI/REF_CLK

M2

M1

M0

# Pin Description

1 Digital Power (Input) - Positive power supply for the digital and analog sections.

2 Ground (Input) - Ground reference.

3 PLL Clock Output (Output) - PLL clock output.

4

Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,

or a status signal, depending on configuration.

5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.

6

7

Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -

XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input

clock. REF_CLK is an input for an externally generated low-jitter reference clock.

8 Mode Select (Input) - M2 is a configurable mode selection pin.

9 Mode Select (Input) - M1 is a configurable mode selection pin.

10 Mode Select (Input) - M0 is a configurable mode selection pin.

4

DS841PP1

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