CS3301-ISZ(2005) Ver la hoja de datos (PDF) - Cirrus Logic
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CS3301-ISZ Datasheet PDF : 16 Pages
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CS3301
DIGITAL CHARACTERISTICS
Parameter
Digital Characteristics
High Level Input Drive Voltage
(Note 17)
Low Level Input Drive Voltage
(Note 17)
Input Leakage Current
Digital Input Capacitance
Rise Times, Digital Inputs Except CLK
Fall Times, Digital Inputs Except CLK
Master Clock Specifications
Master Clock Frequency
(Note 18)
Master Clock Duty Cycle
Master Clock Rise Time
Master Clock Fall Time
Master Clock Jitter (In-Band or Aliased In-Band)
Master Clock Jitter (Out-of-Band)
Symbol
VIH
VIL
IIN
CIN
tRISE
tFALL
fCLK
fDTY
tRISE
tFALL
JTRIB
JTROB
CS3301
Min
Typ
0.6*VD
-
0.0
-
-
+1
-
9
-
-
-
-
2.0 2.048
40
-
-
-
-
-
-
-
-
-
Max
VD
0.8
+10
-
100
100
2.2
60
25
25
300
1
Unit
V
V
µA
pF
ns
ns
MHz
%
ns
ns
ps
ns
Notes: 17. Device is intended to be driven with CMOS logic levels.
18. When CLK is tied to DGND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
t rise
t fa ll
0.9 * VD
0.1 * VD
Figure 2. Digital Input Rise and Fall Times
Input Selection
800 Ω termination
INA only
INB only
INA + INB
MUX1
0
1
0
1
MUX0
0
0
1
1
Gain Selection
x1
x2
x4
x8
x16
x32
x64
reserved
GAIN2
0
0
0
0
1
1
1
1
GAIN1
0
0
1
1
0
0
1
1
Table 1. Digital Selections for Gain and Input Mux Control
GAIN0
0
1
0
1
0
1
0
1
8
DS595F2
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