CDB3318 Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

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CDB3318

Stereo Digital Volume Control

Cirrus Logic 

CS3318

CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT

(Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

CCLK Clock Frequency

RESET Rising Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

(Note 8)

(Note 9)

(Note 9)

Symbol

fsck

tsrs

tcsh

tcss

tscl

tsch

tdsu

tdh

tr2

tf2

Min

0

100

1.0

20

66

66

40

15

-

-

Max

6.0

-

-

-

-

-

-

-

100

100

Unit

MHz

ns

μs

ns

ns

ns

ns

ns

ns

ns

8. Data must be held for sufficient time to bridge the transition time of CCLK.

9. For fsck <1 MHz.

RESET

t srs

CS

t css

CCLK

t scl t sch

t csh

t r2

t f2

MOSI

t dsu

t dh

Figure 2. Control Port Timing - SPI Format

DS693F1

11

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