CS4383-BQ Ver la hoja de datos (PDF) - Cirrus Logic

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CS4383-BQ

114 dB, 192 kHz 8-Channel D/A Converter

Cirrus Logic 

CS4383

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,

CL = 30 pF)

Parameter

CCLK Clock Frequency

Symbol

Min

fsclk

-

Max

M------C----L----K---

2

Unit

MHz

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

tsrs

(Note 20)

tspi

tcsh

tcss

tscl

500

500

1.0

20

--------1---------

MCLK

-

ns

-

ns

-

µs

-

ns

-

ns

CCLK High Time

tsch

--------1---------

MCLK

-

ns

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

tdsu

40

(Note 21)

tdh

15

(Note 22)

tr2

-

(Note 22)

tf2

-

-

ns

-

ns

100

ns

100

ns

Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

23. Data must be held for sufficient time to bridge the transition time of CCLK.

24. For FSCK < 1 MHz.

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

C D IN

t dsu t dh

Figure 4. Control Port Timing - SPI Format

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