CS4392
3.6 Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Tables 5 and 8.
The desired format is selected via the M0 and M1 pins for stand alone mode, and through the DIF2:0 bits
in the control port. For an illustration of the required relationship between the Left/Right Clock, Serial
Clock and Serial Audio Data, see Figures 4-6.
M1
M0
DESCRIPTION
0
0
Left Justified, up to 24-bit data
0
1
I2S, up to 24-bit data
1
0
Right Justified, 16-bit Data
1
1
Right Justified, 24-bit Data
FORMAT
0
1
2
3
FIGURE
4
5
6
6
Table 5. Digital Interface Format, Stand-Alone Mode Options
LRCK
SCLK
SDATA
Left Channel
Right Channel
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Figure 4. Format 0, Left Justified up to 24-Bit Data
LRCK
SCLK
SDATA
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Figure 5. Format 1, I2S up to 24-Bit Data
LRCK
SCLK
SD ATA LSB
Left Channel
Right Channel
MSB-1 -2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
32 clo cks
Figure 6. Format 2, Right Justified 16-Bit Data
Format 3, Right Justified 24-Bit Data
Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
DS459PP3
11