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CRD44600-PH-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

CS44600

LIST OF FIGURES

Figure 1.Performance Characteristics Evaluation Active Filter Circuit ...................................................... 10

Figure 2.XTI Timings ................................................................................................................................. 11

Figure 3.SYS_CLK Timings ...................................................................................................................... 12

Figure 4.PWMOUTxx Timings .................................................................................................................. 12

Figure 5.PS_SYNC Timings ...................................................................................................................... 12

Figure 6.Serial Audio Interface Timing ...................................................................................................... 13

Figure 7.Serial Audio Interface Timing - TDM Mode ................................................................................. 13

Figure 8.Control Port Timing - I²C Format ................................................................................................. 14

Figure 9.Control Port Timing - SPI Format ................................................................................................ 15

Figure 10.CS44600 Pinout Diagram ......................................................................................................... 16

Figure 11.Typical Full-Bridge Connection Diagram .................................................................................. 20

Figure 12.Typical Half-Bridge Connection Diagram .................................................................................. 21

Figure 13.CS44600 Data Flow Diagram (Single Channel Shown) ........................................................... 23

Figure 14.Fundamental Mode Crystal Configuration ................................................................................ 24

Figure 15.3rd Overtone Crystal Configuration .......................................................................................... 25

Figure 16.CS44600 Internal Clock Generation ......................................................................................... 25

Figure 17.I²S Serial Audio Formats ........................................................................................................... 27

Figure 18.Left-Justified Serial Audio Formats ........................................................................................... 27

Figure 19.Right-Justified Serial Audio Formats ......................................................................................... 28

Figure 20.One Line Mode #1 Serial Audio Format .................................................................................... 28

Figure 21.One Line Mode #2 Serial Audio Format .................................................................................... 29

Figure 22.TDM Mode Serial Audio Format ............................................................................................... 29

Figure 23.De-Emphasis Curve .................................................................................................................. 30

Figure 24.Control Port Timing in SPI Mode .............................................................................................. 35

Figure 25.Control Port Timing, I²C Slave Mode Write ............................................................................... 36

Figure 26.Control Port Timing, I²C Slave Mode Read ............................................................................... 36

Figure 27.Recommended CS44600 Power Supply Decoupling Layout .................................................... 38

Figure 28.Recommended CS44600 Crystal Circuit Layout ...................................................................... 39

Figure 29.Recommended PSR Circuit Layout .......................................................................................... 40

Figure 30.PSR Calibration Sequence ....................................................................................................... 43

Figure 31.PWM Output Delay ................................................................................................................... 70

Figure 32.64-Pin LQFP Package Drawing ................................................................................................ 76

6

DS633F1

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