CS44600-CQZR Ver la hoja de datos (PDF) - Cirrus Logic

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CS44600-CQZR

6-Channel Digital Amplifier Controller

Cirrus Logic 

CS44600

LIST OF TABLES

Table 1. Common DAI_MCLK Frequencies .............................................................................................. 24

Table 2. DAI Serial Audio Port Channel Allocations ................................................................................. 26

Table 3. Load Compensation Example Settings ....................................................................................... 31

Table 4. Typical PWM Switch Rate Settings ............................................................................................. 33

Table 5. Digital Audio Interface Formats ................................................................................................... 52

Table 6. Master Integer Volume Settings .................................................................................................. 56

Table 7. Master Fractional Volume Settings ............................................................................................. 57

Table 8. Channel Integer Volume Settings ............................................................................................... 58

Table 9. Channel Fractional Volume Settings ........................................................................................... 59

Table 10. Limiter Attack Rate Settings ...................................................................................................... 61

Table 11. Limiter Release Rate Settings ................................................................................................... 61

Table 12. Channel Load Compensation Filter Coarse Adjust ................................................................... 62

Table 13. Channel Load Compensation Filter Fine Adjust ........................................................................ 62

Table 14. PWM Minimum Pulse Width Settings ........................................................................................ 69

Table 15. Differential Signal Delay Settings .............................................................................................. 69

Table 16. Channel Delay Settings ............................................................................................................. 69

Table 17. Power Supply Sync Clock Divider Settings ............................................................................... 71

Table 18. Decimator Shift/Scale Coefficient Calculation Examples .......................................................... 72

DS633F1

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