CS4614 Ver la hoja de datos (PDF) - Cirrus Logic
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CS4614 Datasheet PDF : 24 Pages
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CS4614
CrystalClear™ SoundFusion™ PCI Audio Accelerator
CPU
North
Bridge
PCI Bus
Host
Memory
South
Bridge
CS4614
Accelerator
CS4297
Audio Out
Audio In
PC/PCI (if used)
Figure 7. AC ‘97 Codec Interface
rameter RAM, and Sample RAM) into host memo-
ry space. This allows the host to directly peek and
poke RAM locations on the device. The relation-
ship between the Base Address Registers in the
CS4614 PCI Configuration Space and the host
memory map is depicted in Figure 8.
The bus mastering PCI bus interface complies with
the PCI Local Bus Specification (version 2.1).
PCI bus transactions
As a target of a PCI bus transaction, the CS4614
supports the Memory Read (from internal registers
or memory), Memory Write (to internal registers
or memory), Configuration Read (from CS4614
configuration registers), Configuration Write (to
CS4614 configuration registers), Memory Read
Multiple (aliased to Memory Read), Memory Read
Line (aliased to Memory Read), and the Memory
Write and Invalidate (aliased to Memory Write)
transfer cycles. The I/O Read, I/O Write, Interrupt
Acknowledge, Special Cycles, and Dual Address
Cycle transactions are not supported.
As Bus Master, the CS4614 generates the Memory
Read Multiple and Memory Write transactions.
The Memory Read, Configuration Read, Configu-
ration Write, Memory Read Line, Memory Write
Device PCI Config. Space
00h Device ID / Vendor ID
04h Status / Command
08h Class Code / Revision
0Ch
Misc. Control
10h Base Address Register 0
14h Base Address Register 1
Direct I/O Registers
(Memory Mapped, 4 kByte)
Direct Memory Interface
(Memory Mapped, 1 MByte)
Figure 8. Host Interface Base Address Registers
DS292PP3
CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM
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