CS4525-CNZR(2008) Ver la hoja de datos (PDF) - Cirrus Logic

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CS4525-CNZR
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

9.5.5 Enable Foldback Floor (EnFloor) .......................................................................................... 75

9.5.6 Ramp Speed (RmpSpd[1:0]) ................................................................................................ 75

9.6 Mixer / Pre-Scale Configuration (Address 06h) ............................................................................. 75

9.6.1 Pre-Scale Attenuation (PreScale[2:0]) .................................................................................. 75

9.6.2 Right Channel Mixer (RChMix[1:0]) ...................................................................................... 76

9.6.3 Left Channel Mixer (LChMix[1:0]) ......................................................................................... 76

9.7 Tone Configuration (Address 07h) ................................................................................................. 76

9.7.1 De-Emphasis Control (DeEmph) .......................................................................................... 76

9.7.2 Adaptive Loudness Compensation Control (Loudness) ....................................................... 76

9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) ....................................................... 77

9.7.4 Treble Corner Frequency (TrebFc[1:0]) ................................................................................ 77

9.7.5 Bass Corner Frequency (BassFc[1:0]) ................................................................................. 77

9.7.6 Tone Control Enable (EnToneCtrl) ....................................................................................... 77

9.8 Tone Control (Address 08h) ........................................................................................................... 78

9.8.1 Treble Gain Level (Treb[3:0]) ................................................................................................ 78

9.8.2 Bass Gain Level (Bass[3:0]) ................................................................................................. 78

9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h) ............................................................. 78

9.9.1 Freeze Controls (Freeze) ...................................................................................................... 78

9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) ....................................................................................... 79

9.9.3 Bass Cross-Over Frequency (BassMgr[2:0]) ........................................................................ 79

9.9.4 Enable Channel B Parametric EQ (EnChBPEq) ................................................................... 79

9.9.5 Enable Channel A Parametric EQ (EnChAPEq) ................................................................... 79

9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) ..................................................... 80

9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) .......................................................... 80

9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) ................................................... 80

9.10.3 Auto-Mute (AutoMute) ........................................................................................................ 80

9.10.4 Enable 2-Way Crossover (En2Way) ................................................................................... 81

9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) ................................................................. 81

9.11 Channel A & B: 2-Way Sensitivity Control (Address 56h) ............................................................ 81

9.11.1 Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0]) ............................ 81

9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) ........................... 82

9.12 Master Volume Control (Address 57h) ........................................................................................ 82

9.12.1 Master Volume Control (MVol[7:0]) .................................................................................... 82

9.13 Channel A and B Volume Control (Address 58h & 59h) .............................................................. 83

9.13.1 Channel X Volume Control (ChXVol[7:0]) ........................................................................... 83

9.14 Sub Channel Volume Control (Address 5Ah) .............................................................................. 83

9.14.1 Sub Channel Volume Control (SubVol[7:0]) ....................................................................... 83

9.15 Mute/Invert Control (Address 5Bh) .............................................................................................. 84

9.15.1 ADC Invert Signal Polarity (InvADC) .................................................................................. 84

9.15.2 Invert Channel PWM Signal Polarity (InvChX) ................................................................... 84

9.15.3 Invert Sub PWM Signal Polarity (InvSub) ........................................................................... 84

9.15.4 ADC Channel Mute (MuteADC) .......................................................................................... 84

9.15.5 Independent Channel A & B Mute (MuteChX) .................................................................... 84

9.15.6 Sub Channel Mute (MuteSub) ............................................................................................ 85

9.16 Limiter Configuration 1 (Address 5Ch) ......................................................................................... 85

9.16.1 Maximum Threshold (Max[2:0]) .......................................................................................... 85

9.16.2 Minimum Threshold (Min[2:0]) ............................................................................................ 85

9.16.3 Peak Signal Limit All Channels (LimitAll) ............................................................................ 86

9.16.4 Peak Detect and Limiter Enable (EnLimiter) ....................................................................... 86

9.17 Limiter Configuration 2 (Address 5Dh) ......................................................................................... 87

9.17.1 Limiter Release Rate (RRate[5:0]) ...................................................................................... 87

9.18 Limiter Configuration 3 (Address 5Eh) ......................................................................................... 87

9.18.1 Enable Thermal Limiter (EnThLim) ..................................................................................... 87

9.18.2 Limiter Attack Rate (ARate[5:0]) ......................................................................................... 87

DS726PP3

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