CS5101A(1995) Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Lista de partido
CS5101A Datasheet PDF : 40 Pages
| |||
CS5101A
ANALOG CHARACTERISTICS (continued)
CS5101A -J,K CS5101A -A,B
Parameter*
Symbol Min Typ Max Min Typ Max
Specified Temperature Range
-
0 to +70
40 to +85
Analog Input
Aperture Time
-
Aperture Jitter
-
Input Capacitance
(Note 6)
Unipolar Mode
-
Bipolar Mode
-
Conversion & Throughput
Conversion Time
(Note 7)
-8 tc
-16 tc
- 25 -
- 100 -
- 25 -
- 100 -
- 320 425 - 320 425
- 200 265 - 200 265
- - 8.12 - - 8.12
- - 16.25 - - 16.25
Acquisition Time
(Note 8)
-8 ta
-16 ta
- - 1.88 - - 1.88
- 2.6 3.75 - 2.6 3.75
Throughput
(Note 9)
-8
-16
Power Supplies
Power Supply Current
(Note 10)
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
Power Consumption
(Notes 10, 11)
(SLEEP High)
(SLEEP Low)
Power Supply Rejection:
(Note 12)
Positive Supplies
Negative Supplies
ftp
ftp
IA+
IA-
ID+
ID-
Pdo
Pds
PSR
PSR
100 - - 100 - -
50 - - 50 - -
- 21 28 - 21 28
- -21 -28 - -21 -28
- 11 15 - 11 15
- -11 -15 - -11 -15
- 320 430 - 320 430
-1- -1-
- 84 -
- 84 -
- 84 -
- 84 -
Units
°C
ns
ps
pF
pF
µs
µs
µs
µs
kHz
kHz
mA
mA
mA
mA
mW
mW
dB
dB
Notes: 6. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
7. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internal loopback (FRN mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay
between the falling edge of HOLD and the start of conversion may add to the apparent conversion time.
This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can
be increased as long as the HOLD sample rate is 100 kHz max.
8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 µs with an 8 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies of 8 MHz or less, fine charge may
be less than 9 clock cycles. This reflects the typ. specification (6 clock cycles + 1.125 µs).
9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
10. All outputs unloaded. All inputs at VD+ or DGND.
11. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
12. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rejection versus frequency.
DS45F2
3
Share Link: 