CS5181 Ver la hoja de datos (PDF) - Cirrus Logic

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CS5181

∆Σ Modulator & 400 kHz to 625 kHz 16-Bit ADC

Cirrus Logic 

CS5181

MCLK

Modulator

Data

SDO

SDO

Reconstructed

Data

Figure 5. Modulator Only Mode Data RTZ Format.

The data from the modulator is output from

SDO/SDO in RTZ (Return to Zero) format. The

circuit in Figure 6 can be used to reconstruct the

data so it can be captured with the rising or falling

edge of MCLK.

Table 2 illustrates the magnitude of the input signal

into the chip versus the ones density out of the

modulator. The table does not take into account the

potential offset and gain errors of the modulator

and their effect on the ones density.

Figure 7 and Figure 8 illustrate magnitude versus

frequency plots of the modulator bitstream when

running at 40.0 MHz.

Fully Differential Bipolar

Input Voltage2

VFS

0

-VFS

Modulator Ones

Density3

75%

50%

25%

Notes: 2. VFS = VREFIN x 1.6

3. Ones density is approximate; it does not

take offset and gain errors into

consideration.

Table 2. Modulator-Only Mode Ones Density.

Figure 7. Magnitude versus frequency spectrum of

modulator bitstream

(MCLK = 40.0 MHz).

SDO

Reconstructed

Data

SDO

Reconstructed

Data

Figure 6. Circuit to Reconstruct

Return-to-Zero (RTZ) Data from

SDO/SDO into Original Modulator Bitstream.

DS250PP1

Figure 8. Expanded view of the magnitude versus fre-

quency spectrum of modulator bitstream

(MCLK = 40 MHz).

11

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