CDB5361 Ver la hoja de datos (PDF) - Cirrus Logic

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CDB5361

114 dB, 192 kHz, Multi-Bit Audio A/D Converter

Cirrus Logic 

CS5361

4.0 APPLICATIONS

4.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5361 must be set to the proper speed

mode via the mode pins, M1 and M0. Refer to Table 1.

M1 (Pin 14)

0

0

1

1

M0 (Pin 13)

0

1

0

1

MODE

Single Speed Mode

Double Speed Mode

Quad Speed Mode

Reserved

Output Sample Rate (Fs)

2 kHz - 51 kHz

50 kHz - 102 kHz

100 kHz - 204 kHz

Table 1. CS5361 Mode Control

4.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously gen-

erated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also

includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other

internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic

0.

4.2.1 Slave Mode

LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the mas-

ter clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master

clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios.

MCLK/LRCK Ratio

SCLK/LRCK Ratio

Single Speed Mode

Fs = 2 kHz to 51 kHz

256x, 512x

32x, 64x, 128x

Double Speed Mode

Fs = 50 kHz to 102 kHz

128x, 256x

32x, 64x

Quad Speed Mode

Fs = 100 kHz to 204 kHz

128x

32x, 64x

Table 2. CS5361 Slave Mode Clock Ratios

16

DS467F2

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