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CS5372-BS

Low-Power High-Performance ∆Σ Modulators

Cirrus Logic 

CS5371/CS5372

the negative half. The INR+ and INR- pins are

switched capacitor ‘rough charge’ inputs for the

INF+ and INF- fine input pins.

The full scale analog signal span is defined by the

voltage applied across the VREF+ and VREF-

pins. A 2.5 volt reference input sets full scale sig-

nals as 5 volts peak-to-peak, or 2.5 volts fully dif-

ferential. Differential inputs increase the dynamic

range of small signals, reducing the gain require-

ments for input amplifier stages by a factor of two

relative to single ended analog inputs.

4.2. Anti-Alias Filters

The CS5371/CS5372 modulator inputs must be

bandwidth limited to ensure modulator loop stabil-

ity and to prevent aliased high-frequency signals.

The modulators are 4th order and so are condition-

ally stable, and can be adversely affected by high

amplitude out-of-band signals. Also, aliasing ef-

fects degrade modulator performance if the analog

inputs are not bandwidth limited since out-of-band

signals can appear in the measurement bandwidth.

The use of a simple single pole low-pass anti-alias

filter on the differential inputs ensures out-of-band

signals are eliminated.

Anti-alias filtering may be accomplished actively

in an amplifier stage ahead of the CS5371/CS5372

modulator, or passively using an RC filter across

the differential rough and fine analog inputs. An

RC filter is recommended, even when using an am-

plifier stage, as it minimizes the ‘charge kick’ that

the driving amplifier sees as switched capacitor

sampling is performed.

The -3 dB corner of the input anti-alias filter should

be set to the internal modulator sampling clock di-

vided by 64. The modulator sampling clock is a di-

vision by 4 of the modulator clock, MCLK. With

MCLK=2.048 MHz the modulator sampling clock

is 512 kHz, requiring an input filter with a -3 dB

corner at 8 kHz.

MCLK Frequency = 2.048 MHz

Sampling Frequency = MCLK / 4 = 512 kHz

-3 dB Filter Corner = Sample Freq / 64 = 8 kHz

RC filter = 8 kHz = 1 / [ 2π * (2 * Rdiff) * Cdiff ]

It should be noted that when using low power mode

(LPWR=1 and MCLK=1.024 MHz) the modulator

sampling clock is 256 kHz, so the -3 dB filter cor-

ner should be scaled down to 4 kHz.

MCLK Frequency = 1.024 MHz

Sampling Frequency = MCLK / 4 = 256 kHz

-3 dB Filter Corner = Sample Freq / 64 = 4 kHz

RC filter = 4 kHz = 1 / [ 2π * (2 * Rdiff) * Cdiff ]

Figure 3 illustrates the CS5372/CS5376 system

connections with input anti-alias filter components.

Filter components on the rough and fine pins

should be identical values for optimum perfor-

mance, with the capacitor values a minimum of

0.01 µF. The rough input can use either X7R or

C0G capacitors, while the fine input requires C0G

type capacitors for optimal linearity. Using X7R

capacitors on the fine inputs will degrade signal to

distortion performance up to 8 dB.

4.3. Input Impedance

Due to the dynamic switched-capacitor input archi-

tecture the input current required from the analog

signal source, and thus the input impedance of the

analog input pins, changes any time MCLK is

changed. The input impedance of the rough charge

inputs, INR+ and INR-, is [1 / (f * C)] where f is the

modulator clock frequency, MCLK, and C is the in-

ternal sampling capacitor. A 2.048 MHz modula-

tor clock yields a rough input impedance of

approximately [1 / (2.048 MHz)*(20 pF)], or about

24 kohms.

Internal to the modulator the rough charge inputs

pre-charge the sampling capacitor used by the fine

inputs, therefore the effective input impedance of

the fine inputs is orders of magnitude above the im-

pedance of the rough inputs.

10

DS255PP2

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