CS5371-BSZ Ver la hoja de datos (PDF) - Cirrus Logic

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CS5371-BSZ

Low-power, High-performance ∆Σ Modulators

Cirrus Logic 

CS5371 CS5372

SWITCHING CHARACTERISTICS Notes:TA = -40 C to +85 C; VA+ = +5V or +2.5V ± 5%; VA-

= 0V or -2.5V ± 5%; VD = +5V or +3.3V ± 5%; Digital Inputs: Logic 0 = 0V, Logic 1 = VD; CL = 50 pF

Parameter

MCLK Frequency

MCLK Duty Cycle

MCLK Jitter (In-band or aliased in-band)

MCLK Jitter (Out-of-band)

Rise Times:

Any Digital Input

Any Digital Output

Fall Times:

Any Digital Input

Any Digital Output

MSYNC Setup Time to MCLK falling

MSYNC Hold Time after MCLK falling

MCLK rising to Valid MFLAG

MCLK rising to Valid MDATA

Symbol

(Note 17)

fc

(Note 18)

(Note 18)

(Note 19)

trisein

triseout

tfallin

tfallout

tmss

tmsh

tmfh

tmdv

Min

Typ

Max

0.1 2.048

2.2

40

-

60

-

-

300

-

-

1

-

-

50

-

50

100

-

-

50

-

50

100

20

-

-

20

-

-

-

35

65

-

60

90

Unit

MHz

%

ps

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes: 17. If MCLK is removed, the CS5372 enters a micro power state.

18. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.

19. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.

t risein

t fallin

0.9 * VD

0.1 * VD

t riseout

Figure 1. Rise and Fall Times

t fallout

0.9 * VD

0.1 * VD

MCLK

t mss

MSYNC

MDATA

MFLAG

6

t msh

t mdv

VALID DATA

t mdv

VALID DATA

t mfh

Figure 2. CS5372 Interface Timing

DS255F3

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