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CS5331A

8-Pin, Stereo A/D Converter for Digital Audio

Cirrus Logic 

3.1.7

3.1.8

CS5330A/31A

Analog Connections

Figure 1 shows the analog input connections. The analog inputs are presented to the modula-tors via the

AINR and AINL pins. Each analog input will accept a maximum of 4 Vpp centered at +2.4 V.

The CS5330A/31A samples the analog inputs at 128 × Fs, 6.144 MHz for a 48 kHz sample-rate. The dig-

ital filter rejects all noise above 29 kHz except for frequencies right around 6.144 MHz ±21.7 kHz (and

multiples of 6.144 MHz). Most audio signals do not have significant energy at 6.144 MHz. Nevertheless,

a 150 Ω resistor in series with each analog input and a 10 nF capacitor across the inputs will attenuate

any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modula-

tors. The use of capacitors which have a large voltage coefficient must be avoided since these will de-

grade signal linearity. It is also important that the self-resonant frequency of the capacitor be well above

the modulator sampling frequency. General purpose ceramics and film capacitors do not meet these re-

quirements. However, NPO and COG capacitors are acceptable. If active circuitry precedes the ADC, it

is recom-mended that the above RC filter is placed between the active circuitry and the AINR and AINL

pins. The above example frequencies scale linearly with Fs.

High-Pass Filter

The operational amplifiers in the input circuitry driving the CS5330A/31A may generate a small DC offset

into the A/D converter. The CS5330A/31A includes a high pass filter after the decimator to remove any

DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between

de-vices in a multichannel system.

The characteristics of this first-order high pass filter are outlined in the “Digital Filter Characteristics” on

page 6

3.1.9

Initialization and Power-Down

The Initialization and Power-Down sequence is shown in Figure 4. Upon initial power-up, the digital filters

and delta-sigma modulators are reset and the internal voltage reference is powered down. The device will

remain in the Initial Power-Down mode until MCLK is presented. Once MCLK is available, the

CS5330A/31A will make a master/slave mode decision based upon the presence/absence of a 47 kohm

pull-down resistor on SDATA as shown in Figure 1. The master/slave decision is made during initial pow-

er-up as shown in Figure 4.

In master mode, SCLK and LRCK are outputs where the MCLK/LRCK frequency ratio is 256x. LRCK will

appear as an output 127 MCLK cycles into the initialization sequence. At this time, power is applied to the

internal voltage reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static low

during the initialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235

ms at a 48 kHz output sample rate).

In slave mode, SCLK and LRCK are inputs where the MCLK/LRCK frequency ratio must be either 256x,

384x, or 512x. Once the MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK

period to determine the MCLK/LRCK frequency ratio. At this time, power is applied to the internal voltage

reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static high during the ini-

tialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kHz

sample rate).

DS138F5

11

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