CS5529 Ver la hoja de datos (PDF) - Cirrus Logic

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CS5529

16-bit, Programmable ∆Σ ADC with 6-bit Latch

Cirrus Logic 

CS5529

SWITCHING CHARACTERISTICS (TA = 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%;

Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF)

Parameter

Symbol Min Typ Max Unit

Master Clock Frequency:

Master Clock Duty Cycle

Rise Times

Fall Times

Start-up

Oscillator Start-up Time

Power-on Reset Period

External Clock or Internal Oscillator

XIN

(Note19)

(Note 20) trise

Any Digital Input Except SCLK

SCLK

Any Digital Output

(Note 20) trise

Any Digital Input Except SCLK

SCLK

Any Digital Output

XTAL = 32.768 kHz (Note 21) tost

tpor

Serial Port Timing

Serial Clock Frequency

Serial Clock

SDI Write Timing

CS Enable to Valid Latch Clock

Data Set-up Time prior to SCLK rising

Data Hold Time After SCLK Rising

SCLK Falling Prior to CS Disable

SDO Read Timing

CS to Data Valid

SCLK Falling to New Data Bit

CS Rising to SDO Hi-Z

SCLK

Pulse Width High t1

Pulse Width Low t2

t3

t4

t5

t6

t7

t8

t9

30 32.768 100 kHz

40

-

60

%

-

-

1.0 µs

-

-

100 µs

-

50

-

ns

-

-

1.0 µs

-

-

100 µs

-

50

-

ns

-

500

-

ms

-

1002

-

XIN

cycles

0

-

250

-

250

-

2 MHz

-

ns

-

ns

50

-

50

-

100

-

100

-

-

ns

-

ns

-

ns

-

ns

-

-

150 ns

-

-

150 ns

-

-

150 ns

Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for

increased throughput.

20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

8

DS246F5

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