CS61310(2003) Ver la hoja de datos (PDF) - Cirrus Logic

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CS61310
(Rev.:2003)

T1 Line Interface Unit

Cirrus Logic 

CS61310

3. ARBITRARY WAVEFORM GENERATION ............................................................................ 17

4. PIN DESCRIPTION ................................................................................................................. 20

5. PACKAGE DIMENSIONS ...................................................................................................... 25

6. APPLICATIONS ..................................................................................................................... 27

LIST OF FIGURES

Figure 1. Signal Rise and Fall Characteristics ............................................................................ 7

Figure 2. Recovered Clock and Data Switching Characteristics ................................................. 7

Figure 3. Transmit Clock and Data Switching Characteristics .................................................... 7

Figure 4. Serial Port Write Timing Diagram ................................................................................ 8

Figure 5. Serial Port Read Timing Diagram ................................................................................ 8

Figure 6. Typical Pulse Shape for DS-1 ...................................................................................... 9

Figure 7. Minimum Input Jitter Tolerance of Receiver .............................................................. 10

Figure 8. Typical Jitter Transfer Function .................................................................................. 11

Figure 9. LATN Pulse Width encoding ...................................................................................... 11

Figure 10. Input/Output Timing (showing address 0x10) ............................................................ 13

Figure 11. Phase Definition of Arbitrary Waveforms ................................................................... 17

Figure 12. Example of Summing of Waveforms .......................................................................... 17

Figure 13. Hardware Mode Operation ......................................................................................... 27

Figure 14. Matched Impedence Output Configuration ................................................................ 28

LIST OF TABLES

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Pulse Shape Selection and Transformer Requirements ............................................... 9

Data Output/Clock Relationship.................................................................................. 10

Register Map............................................................................................................... 13

Register 16 Decoding ................................................................................................. 15

CS61310 Diagnostic Mode Availability ....................................................................... 18

Transformer Specification ........................................................................................... 19

Recommended Tranformers for the CS61310 ............................................................ 19

DS440F1 FEB ‘03

3

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