CDB8416 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB8416 Datasheet PDF : 42 Pages
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CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol Min Typ Max
CCLK Clock Frequency
(Note 9)
fsck
0
-
6.0
CS High Time Between Transmissions
tcsh
1.0
-
-
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
tcss
tscl
(Note 10)
tsch
tdsu
(Note 11)
tdh
tpd
tr1
tf1
(Note 12)
tr2
(Note 12)
tf2
20
-
-
66
-
-
MAX ((1/256 FS + 8), 66)
40
-
-
15
-
-
-
-
50
-
-
25
-
-
25
-
-
100
-
-
100
Units
MHz
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate.
10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsck < 1 MHz.
CS
t css
CCLK
t r2
CDIN
CDOUT
t scl t sch
t f2
t dsu
t dh
t pd
Figure 3. SPI Mode Timing
t csh
DS580F5
7
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