CS8920A Ver la hoja de datos (PDF) - Cirrus Logic
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CS8920A Datasheet PDF : 144 Pages
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CS8920A
2.2 Pin Description
ISA Bus Interface
Symbol Pin Number
SA0-SA8
SA9-SA11
SA12-SA16
58-66
80-82
84-88
LA17-LA23
45-51
BALE
57
SD0-SD3
SD4-SD7
SD8-SD11
SD12-SD15
RESET
96-99
102-105
27-24
21-18
114
AEN
91
MEMR
29
MEMW
28
MCS16
44
REFRESH
83
IOR
89
IOW
90
Type
I
I
I
B24
I
I
I
I
OD24
I
I
I
Description
System Address Bus: Address decoding for the ISA addresses including
Boot PROM and memory addresses. SA0-SA15 are used for I/O read/write
operations. SA0-SA16 are used in for Memory read and write operations.
Latchable Address Bus: Address decoding for the buffered version of the
upper ISA address bits. Used for early address decode. Latched on the
trailing edge of the BALE signal.
Buffered Address Latch Enable: Rising edge signals the CS8920A to
decode the LA17:LA23. The trailing edge of BALE is used to latch the
address and hold it for the duration of the current bus cycle.
System Data Bus: Bi-directional 16-bit System Data Bus used to transfer
data between the CS8920A and the host.
Reset: Active-high asynchronous input used to reset the CS8920A. Must
be stable for at least 400 ns before the CS8920A recognizes the signal as
a valid reset.
Address Enable: When TEST is high, the active-high AEN input indicates
to the CS8920A that the system DMA controller has control of the ISA bus.
When AEN is high, the CS8920A will not respond to an IO or Memory
space access.
Memory Read: Active-low input indicates that the host is executing a
Memory Read operation.
Memory Write: Active-low input indicates that the host is executing a
Memory Write operation.
Memory Chip Select 16: Open-drain, active-low output generated by the
CS8920A when it recognizes an address on the ISA bus that corresponds
to its assigned Memory space (CS8920A must be in Memory Mode with
the MemoryE bit (Register 17, BusCTL, Bit A) set for MCS16 to go active).
Tri-stated when not active.
Refresh: Active-low input indicates to the CS8920A that a DRAM refresh
cycle is in progress. When REFRESH is low, MEMR, MEMW, IOR, IOW,
DMACK0, DMACK1, and DMACK2 are ignored.
I/O Read: When IOR is low and a valid address is detected, the CS8920A
outputs the contents of the selected 16-bit I/O register onto the System
Data Bus. IOR is ignored if REFRESH is low.
I/O Write: When IOW is low and a valid address is detected, the
CS8920A writes the data on the System Data Bus into the selected 16-bit
I/O register. IOW is ignored if REFRESH is low.
Pin Types:
dI = Differential Input Pair
I
dO = Differential Output Pair
O
B = Bi-Directional with Tri-State Output P
OD = Open Drain Output
= Input
= Output
= Power
G = Ground
ts = Tri-State
w = Internal Weak Pullup
Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).
10
DS238PP2
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