CS8952(2001) Ver la hoja de datos (PDF) - Cirrus Logic
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CS8952 Datasheet PDF : 82 Pages
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CS8952
100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES
Parameter
Symbol
Min
RX_CLK Period
tP
-
RX_CLK Pulse Width
tWL, tWH
-
RXD[3:0],RX_ER/RXD4,RX_DV setup to rising
tSU
10
edge of RX_CLK
RXD[3:0],RX_ER/RXD4,RX_DV hold from rising
tHD
10
edge of RX_CLK
CRS to RXD latency
4B Aligned tDLAT
2
5B Aligned
2
“Start of Stream” to CRS asserted
“End of Stream” to CRS de-asserted
“Start of Stream” to COL asserted
“End of Stream” to COL de-asserted
RX_EN asserted to RX_DV, RXD[3:0] valid
RX_EN de-asserted to RX_DV, RXD[3:0].
RX_ER/RXD4 in high impedance state
tCRS1
-
tCRS2
-
tCOL1
-
tCOL2
-
tEN
-
tDIS
-
Typ
40
20
-
-
3-6
3-6
10
-
-
-
TBD
TBD
Max
Unit
-
ns
-
ns
-
ns
-
ns
8
BT
8
11
BT
21
BT
11
BT
21
BT
-
ns
-
ns
RX+/-
CRS
COL
RX_EN
RX_DV
RXD[3:0],
RX_ER/RXD4
RX_CLK
Start of
Stream
tCRS1
tCOL1
End of
Stream
tCRS2
tCOL2
tEN
tRLAT
tP
tWL tWH
tSU tHD
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
IN
OUT
OUT
tDIS
IN
OUT
OUT
OUT
9
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