CS8416-CSZR Ver la hoja de datos (PDF) - Cirrus Logic
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CS8416-CSZR Datasheet PDF : 60 Pages
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3. PIN DESCRIPTION - HARDWARE MODE
3.1 TSSOP Pin Description
CS8416
RXP3
RXP2
RXP1
RXP0
RXN
VA
AGND
FILT
RST
RXSEL1
RXSEL0
TXSEL1
TXSEL0
NV / RERR
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
Top-Down View
17
28-pin SOIC/TSSOP
13
Package
16
14
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
TX
C
U
RCBL
96KHZ
AUDIO
Pin Name
VA
VD
VL
AGND
DGND
RST
FILT
RXP0
RXP1
RXP2
RXP3
RXN
Pin #
6
23
21
7
22
9
8
4
3
2
1
5
Pin Description
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little
noise as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
Digital Power (Input) – Digital core power supply. Nominally +3.3 V
Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog
ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter”
on page 53 for more information on the PLL and the external components.
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The
select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left
floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49
for recommended input circuits.
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-
ended operation this should be AC coupled to ground through a capacitor. See “External
AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.
16
DS578F3
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