CS8416-IS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8416-IS Datasheet PDF : 48 Pages
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CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(TA = 25 °C for suffixes ‘CS’ & ’CZ’, TA = -40 to 85 °C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5
V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid
Master Mode
(Note 5) tdpd
-
-
15
ns
RMCK to OSCLK active edge delay
RMCK to OLRCK delay
OSCLK and OLRCK Duty Cycle
(Note 5) tsmd
0
-
10
ns
(Note 6) tlmd
0
-
10
ns
-
50
-
%
Slave Mode
OSCLK Period
tsckw
36
-
OSCLK Input Low Width
tsckl
14
-
OSCLK Input High Width
tsckh
14
-
OSCLK Active Edge to OLRCK Edge
(Notes 5,6,7) tlrckd
10
-
OSCLK Edge Setup Before OSCLK Active-Edge (Notes 5,6,8) tlrcks
10
-
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 5. In Software mode the active edges of OSCLK are programmable.
6. In Software mode the polarity of OLRCK is programmable.
7. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
8. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
OSCLK
(output)
OLRCK
(output)
RMCK
(output)
t smd
t lm d
Figure 1. Audio Port Master Mode Timing
OLRCK
(input)
OSCLK
(input)
t lrckd
t lrcks
SDOUT
t sckh
tsckl
t sckw
tdpd
Figure 2. Audio Port Slave Mode and Data Input Timing
DS578PP2
7
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