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CX11627-11

AccessRunner™ ADSL-USB Modem Device Set

Conexant Systems 

AccessRunner ADSL-USB Modem Device Set Data Sheet

Label

Pin

RXSOC0

168

RCLKAS0

169

RDATAS0

167

TXSOC0

173

TCLKLS0

174

TDATLS0

170

AFE_RST#

161

(GPIO08)

LD_PC

166

(GPIO13)

LD_OH_DET

156

(GPIO05)

PAIR_SEL

3

(GPIO21)

BCLKIO (GPIO38) 30

I2C_SCL (GPIO16) 11

I2C_SDA (GPIO15) 12

TRST#

31

TCK

32

TMS

33

TDI

34

TDO

35

Table 3-1. P5200 UIC Hardware Signal Definitions (Continued)

I/O

I/O Type

Signal Name/Description

CX11627 ADDP SERIAL CHANNEL INTERFACE

I

Itpu

Receive ATM0 Start of Cell. Connect to ADDP RXSOC0.

I

Itpu

Receive AS0/ATM0 Data Clock. Connect to ADDP R_CLK_LS0.

I

Itpu

Receive AS0/ATM0 Serial Data. Connect to ADDP R_DAT_LS0.

O

Otts4

Transmit ATM0 Start of Cell. Connect to ADDP TXSOC0.

I

It

Transmit LS0/ATM0 Data Clock. Connect to ADDP T_CLK_LS0.

O

Otts4

Transmit LS0/ATM0 Serial Data. Connect to ADDP T_DAT_LS0.

CX20431 AFE AND CX20441 LD CONTROL

O

Ot4

AFE Reset. Active low reset output to the AFE and the LD. Connect

to AFE POR# and to LD PWRDWN#.

O

Ot4

Line Driver Power Control. Optionally, connect to LD PWRDWN#

when it is desired to power down only the LD.

LINE INTERFACE

I

It

Off-Hook Detect. Active low; indicates POTS off-hook event. Used

for G.lite Mode only. Connect to off-hook detector circuit.

O

Itpu/Ot4

Inner/Outer Pair Select. Connect to wire-pair selection circuit.

O

Itpu/Ot4

Receive Pad. Connect to receive pad circuitry in hybrid.

SERIAL EEPROM INTERFACE

O

Ot4

Serial EEROM Clock. Connect to EEPROM clock input.

I

Itpu

Serial EEROM Data. Connect to EEPROM data line.

JTAG INTERFACE

I

Itpu

JTAG Reset. A high-to-low transition on this signal forces the TAP

controller into a logic reset state. This pin has an internal pullup, and it

conforms to IEEE 1149.1 JTAG specification.

I

It

JTAG Test Clock. This is the boundary scan clock input signal. This

pin has an internal pullup, and it conforms to IEEE 1149.1 JTAG

specification.

I

Itpu

JTAG Test Mode Select. This signal controls the operation of the

TAP controller. This pin has an internal pull-up, and it conforms to

IEEE 1149.1 JTAG specification.

I

Itpu

JTAG Test Input. This signal contains serial data that is shifted in on

the rising edge of TCK. The pin has an internal pullup, and it conforms

to IEEE 1149.1 JTAG specification.

O

Otts4

JTAG Test Output Data. This is the three-stateable boundary scan

data output signal from the MCU, and it is shifted out on the falling

edge of TCK. It conforms to IEEE 1149.1 JTAG specification.

100427B

Conexant

3-5

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