CXB1577Q Ver la hoja de datos (PDF) - Sony Semiconductor
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CXB1577Q Datasheet PDF : 22 Pages
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CXB1577Q
AC Characteristics
VCC = GND, VEE = –5V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = open,
or VCC = GND, VEE = –3.3V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = GND
Item
Symbol
Conditions
Min.
Typ. Max. Unit
Maximum input voltage amplitude Vmax single-ended input
1600
mVp-p
Amplifier gain (excluding the output buffer) GL
52
dB
Identification maximum voltage
amplitude of alarm level
VmaxA1
SW pad: Low,
single-ended input
20
VmaxA2
SW pad: Open High,
single-ended input
40
mVp-p
SD/SDB hysteresis width
∆P1
SW pin: Low,
at default alarm level
3
6
7
dB
∆P2
SW pin: Open High,
at default alarm level
3
6
7
Alarm setting level for default
UP/DOWN pin: open,
Vdef VEEI = VEE,
7.0
8.4
9.7 mV
Differential voltage input
Q/QB rise time
Q/QB fall time
TrQ 20% to 80%
TfQ
50Ω to VTT
230
350
ps
230
350
SD-TTL/SDB-TTL rise time
TrSDT VEE + 0.8V to VEE + 2.0V
10
SD-TTL/SDB-TTL fall time
TfSDT CL = 10pF
10
SD-ECL/SDB-ECL rise time
SD-ECL/SDB-ECL fall time
TrSDE
TfSDE
20% to 80%
When Vcc – VEE = 5.0V,
510Ω to VEE,
when Vcc – VEE = 3.3V,
270Ω to VEE
1.6
ns
1.6
Propagation delay time
SD response assert time
SD response deassert time
TPD
Tas
∗1
Tdas ∗2
0.4
1.9
0
100
2.3
100
SD response assert time for alarm
level default
Tasd ∗3
0
100
µs
SD response deassert time for alarm
level default
Tdasd
∗4
2.3
100
∗1 VUP – VDOWN = 100mV, Vin = 100mVp-p (single ended), SW pin: High, peak hold capacitance (CAP2,
CAP3 pins) of 470pF, connect VEEI to VEE.
∗2 VUP – VDOWN = 100mV, Vin = 1Vp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3
pins) of 470pF, connect VEEI to VEE.
∗3 Vin = 50mVp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE.
∗4 Vin = 1Vp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE.
–9–
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