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CXD2453Q Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD2453Q
Sony
Sony Semiconductor Sony
CXD2453Q Datasheet PDF : 21 Pages
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CXD2453Q
• System clear pin (XCLR)
All internal circuits are initialized when the XCLR (Pin 78) is L. Always make sure to initialize all internal circuits
when the power has been turned on.
• Serial data interface
Operating mode and other settings in this IC are performed by serial data. When the power is turned on, all
data are set to the default values when the internal circuits are initialized. When the power supply is turned on,
the value of SDAT is read with the rise of SCLK in groups of 16 bits consisting of 8 address bits and 8 data bits
as shown in the Timing Chart below. The data that has been read is enabled by being transferred to the
register corresponding to each address 10 clocks after the rise of SCLK of the 16th bit.
The Timing Chart and Data Format during transmission of serial data are as shown below.
Timing Chart
SCTL (Pin 8)
SCLK (Pin 6)
SDAT (Pin 7)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Address (8 bits)
Data (8 bits)
Data Format
Address
Data
D15 to D8 D7
D6
D5
D4
D3
D2
D1
D0
Settings
F0
— PLP10 PLP9 PLP8 PLL counter frequency
F1
PLP7 PLP6 PLP5 PLP4 PLP3 PLP2 PLP1 PLP0 division ratio
F2
HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 Screen horizontal position
F3
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 Screen vertical position
F4
INV SHP3 SHP2 SHP1 SHP0 CXA2112R S/H control
F5
— VPOL HPOL VSCN HSCN SLXG SLSX Operating mode, etc.
F6
HB
VB SLLAP IRD10 IRD9 IRD8 Operating mode, etc./
F7
IRD7 IRD6 IRD5 IRD4 IRD3 IRD2 IRD1 IRD0 IRACT fall position
F8
— IRU10 IRU9 IRU8
IRACT rise position
F9
IRU7 IRU6 IRU5 IRU4 IRU3 IRU2 IRU1 IRU0
FA
— ORRS1 ORRS0 ORP10 ORP9 ORP8 ORACT reset cycle/
FB
ORP7 ORP6 ORP5 ORP4 ORP3 ORP2 ORP1 ORP0 ORACT division frequency
FC
— ORD10 ORD9 ORD8
ORACT fall position
FD
ORD7 ORD6 ORD5 ORD4 ORD3 ORD2 ORD1 ORD0
FE
— ORU10 ORU9 ORU8
ORACT rise position
FF
ORU7 ORU6 ORU5 ORU4 ORU3 ORU2 ORU1 ORU0
Note) —: Don't care
– 10 –

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