CY14B256P(2013) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B256P
(Rev.:2013)

256-Kbit (32 K × 8) Serial (SPI) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256P

Figure 3. System Configuration using SPI nvSRAM

SCK

MOSI

M IS O

uC ontroller

CS1

HOLD1

CS2

HOLD2

SCK SI

SO

CY14B256P

CS

HOLD

SCK SI

SO

CY14B256P

CS

HOLD

SPI Modes

CY14B256P device may be driven by a microcontroller with its

SPI peripheral running in either of these two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

CS

SCK

SI

Figure 4. SPI Mode 0

012 345 67

7 654321 0

MSB

LSB

The two SPI modes are shown in Figure 4 and Figure 5. The

status of clock when the bus master is in standby mode and not

transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the

either Mode 0 or Mode 3. CY14B256P detects the SPI mode

from the status of SCK pin when the device is selected by

bringing the CS pin LOW. If SCK pin is LOW when the device is

selected, SPI Mode 0 is assumed and if SCK pin is HIGH,

CY14B256P works in SPI Mode 3.

Figure 5. SPI Mode 3

CS

SCK

012 34567

SI

7 654321 0

MSB

LSB

Document Number: 001-53881 Rev. *J

Page 7 of 37

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