CY2213(2012) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY2213 Datasheet PDF : 16 Pages
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CY2213
An alternative termination scheme can be used to drive a standard PECL fanout buffer.
PECL
Differential
Driver
Figure 8. Output Driving Load (-3)
VDD
Measurement Point
79
50
135
135
50
79
79
79
Measurement Point
The PECL differential driver is designed for low voltage, high
frequency operation. It significantly reduces the transient
switching noise and power dissipation when compared to
conventional CMOS drivers. The nominal value of the channel
impedance is 50. The pull up and pull down resistors provide
matching channel termination. The combination of the
differential driver and the output network determines the voltage
swing on the channel. The output clock is specified at the
measurement point indicated in Figure 6 on page 8 and Figure 7
on page 8.
Signal Waveforms
A physical signal that appears at the pins of the device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. This section defines the voltage and timing
waveforms for the input and output pins of the CY2213. The
Device Characteristics tables list the specifications for the device
parameters that are defined here.
Input and Output voltage waveforms are defined as shown in
Figure 9. Rise and fall times are defined as the 20% and 80%
measurement points of VOHmin – VOLmax.
The device parameters are defined in Table 3. Figure 10 on page
10 shows the definition of long term duty cycle, which is simply
the CLK waveform high time divided by the cycle time (defined
at the crossing point). Long term duty cycle is the average over
many (>10,000) cycles. DC is defined as the Output Clock Long
Term Duty Cycle.
Table 3. Definition of Device Parameters
Parameter
VOH, VOL
VIH, VIL
tCR, tCF
Definition
Clock output high and low voltages
VDD LVCMOS input high and low voltages
Clock output rise and fall times
Figure 9. Voltage Waveforms
V(t)
tCF
tCR
VOHmin
80%
20%
VOLmax
Document Number: 38-07263 Rev. *H
Page 9 of 16
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