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CY22313

Two-PLL Clock Generator with Direct Rambus™ (Lite) Support

Cypress Semiconductor 

CLK

CLKB

CLK

CLKB

CLK

CLKB

CLK

CLKB

tCYCLE,i

tCYCLE,i+1

t8 = tCYLCE,i – tCYCLE,i+1 over 10000 consecutive cycles

Figure 5. CLK, CLKB Cycle-to-Cycle Jitter

t4CYCLE,i

t4CYCLE,i+1

t8 = t4CYCLE,i - t4CYCLE,i+1 over 10000 consecutive cycles

Figure 6. CLK, CLKB 4-Cycle-to-Cycle Jitter

tCYCLE

t9 = tCYCLE,max – tCYCLE,min over 10000 cycles

Figure 7. CLK, CLKB Long-term Jitter

Cycle i

Cycle i+1

tPW+,i

tCYCLE,i

tPW+,i+1

tCYCLE,i+1

t10 = tPW+,i – tPW+,i+1

Figure 8. CLK, CLKB Duty Cycle Error

CY22313

Document #: 38-07434 Rev. *E

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