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CY22393

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Cypress Semiconductor 

CY22393

CY22394

CY22395

Figure 2. Data Frame Architecture

SDAT Write

Multiple

Contiguous

Registers

1 Bit

1 Bit Slave

R/W = 0 ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

7-bit

Device

Address

8-bit

Register

Address

(XXH)

8-bit

Register

Data

(XXH)

8-bit

Register

Data

(XXH+1)

8-bit

Register

Data

(XXH+2)

Start Signal

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

8-bit

Register

Data

(FFH)

8-bit

Register

Data

(00H)

SDAT Read

1 Bit

1 Bit Slave

R/W = 1 ACK

1 Bit

Slave

ACK

Current

7-bit

Address

Device

Address

Read Start Signal

8-bit

Register

Data

1 Bit

Master

ACK

Stop Signal

SDAT Read

Multiple

Contiguous

Registers

1 Bit

1 Bit Slave

R/W = 0 ACK

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

7-bit

Device

Address

8-bit

Register

Address

(XXH)

7-bit

Device

Address

+R/W=1

8-bit

Register

Data

(XXH)

8-bit

Register

Data

(XXH+1)

Start Signal

Repeated

Start bit

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

8-bit

Register

Data

(FFH)

8-bit

Register

Data

(00H)

Figure 3. Data Valid and Data Transition Periods

Data Valid

Transition

to next Bit

SDAT

1 Bit

Slave

ACK

Stop Signal

1 Bit

Master

ACK

Stop Signal

tDH tSU

VIH

SCLK

VIL

CLKHIGH

CLKLOW

Document #: 38-07186 Rev. *C

Page 10 of 17

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