CY2305C
CY2309C
Electrical Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Electrical characteristics table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX industrial/automotive-A
temperature devices.
Parameter
Description
Test Conditions
Min
VIL
Input LOW voltage[9]
–
VIH
Input HIGH voltage[9]
2.0
IIL
Input LOW current
VIN = 0 V
–
IIH
Input HIGH current
VIN = VDD
–
VOL
Output LOW voltage[10]
IOL = 8 mA (–1)
–
IOH =12 mA (–1H)
VOH
Output HIGH voltage[10]
IOH = –8 mA (–1)
2.4
IOL = –12 mA (–1H)
IDD (PD mode) Power-down supply current
REF = 0 MHz
–
IDD
Supply current
Unloaded outputs at 66.67 MHz,
–
SEL inputs at VDD
Max
0.8
–
50
100
0.4
–
25
35
Unit
V
V
A
A
V
V
A
mA
Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Switching characteristics table for CY2305CSXC-1 and CY2309CSXC-1 commercial temperature devices. All parameters are
specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ Max Unit
t1
Output frequency
30 pF load
10 pF load
10
–
100 MHz
10
133.33 MHz
tDC
Output duty cycle[10] = t2 t1
Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout 50 MHz
45
50
55
%
t3
Rise time[10]
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
t4
Fall time[10]
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
t5
Output-to-output skew[10]
All outputs equally loaded
–
–
200
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge[10]
Measured at VDD/2
–
0
±350
ps
t6B
t7
tJ
tLOCK
Delay, REF rising edge to
CLKOUT rising edge[10]
Measured at VDD/2. Measured in
1
PLL Bypass mode, CY2309C device
only.
Device-to-device skew[10]
Measured at VDD/2 on the CLKOUT
–
pins of devices
Cycle-to-cycle jitter, peak[10]
Measured at 66.67 MHz, loaded
–
outputs
PLL lock time[10]
Stable power supply, valid clock
–
presented on REF pin
5
8.7
ns
0
700
ps
50
175
ps
–
1.0
ms
Notes
9. .REF input has a threshold voltage of VDD/2.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *K
Page 7 of 17
[+] Feedback