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CY2308

3.3V Zero Delay Buffer

Cypress Semiconductor 

CY2308

Available CY2308 Configurations

Device

CY2308–1

CY2308–1H

CY2308–2

CY2308–2

CY2308–3

CY2308–3

CY2308–4

CY2308–5H

Feedback From

Bank A or Bank B

Bank A or Bank B

Bank A

Bank B

Bank A

Bank B

Bank A or Bank B

Bank A or Bank B

Bank A Frequency

Reference

Reference

Reference

2 X Reference

2 X Reference

4 X Reference

2 X Reference

Reference /2

Bank B Frequency

Reference

Reference

Reference/2

Reference

Reference or Reference[5]

2 X Reference

2 X Reference

Reference /2

Zero Delay and Skew Control

Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins

To close the feedback loop of the CY2308, the FBK pin is driven

from any of the eight available output pins. The output driving the

FBK pin drives a total load of 7 pF plus any additional load that

it drives. The relative loading of this output to the remaining

outputs adjusts the input-output delay. This is shown in the

Figure 2.

For applications requiring zero input-output delay, all outputs

including the one providing feedback is equally loaded.

If input-output delay adjustments are required, use the Zero

Delay and Skew Control graph to calculate loading differences

between the feedback output and remaining outputs.

For zero output-output skew, outputs are loaded equally. For

further information on using CY2308, refer to the application note

“CY2308: Zero Delay Buffer.”

Note

5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.

Document Number: 38-07146 Rev. *F

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