CY7C024AV(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C024AV
(Rev.:1999)

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

PRELIMINARY

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Switching Waveforms (continued)

Busy Timing Diagram No.1 (CE Arbitration)[42]

CELValid First:

ADDRESS L,R

ADDRESS MATCH

CEL

CER

BUSYR

CER Valid First:

ADDRESS L,R

tPS

tBLC

tBHC

ADDRESS MATCH

CER

CE L

BUSYL

tPS

tBLC

tBHC

Busy Timing Diagram No.2 (Address Arbitration)[42]

Left Address Valid First:

ADDRESS L

ADDRESSR

BUSY R

tRC or tWC

ADDRESS MATCH

tPS

tBLA

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSY L

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

ADDRESS MISMATCH

tBHA

Note:

42. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

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