CY7C024-25JXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C024-25JXC
Cypress Semiconductor
CY7C024-25JXC Datasheet PDF : 21 Pages
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CY7C024/0241
CY7C025/0251
Switching Characteristics Over the Operating Range (continued)[13]
7C024/0241–15 7C024/0241–25 7C024/0241–35 7C024/0241–55
7C025/0251–15 7C025/0251–25 7C025/0251–35 7C025/0251–55
Parameter
Busy Timing[19]
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tBLA
BUSY LOW from Address
15
20
20
45
ns
Match
tBHA
BUSY HIGH from Address
15
20
20
40
ns
Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH
(Slave)
tBDD[20]
BUSY HIGH to Data Valid
Interrupt Timing[19]
15
20
15
20
5
5
0
0
13
20
Note 20
Note 20
20
40
ns
20
35
ns
5
5
ns
0
0
ns
30
40
ns
Note 20
Note 20 ns
tINS
INT Set Time
tINR
INT Reset Time
Semaphore Timing
15
20
25
30
ns
15
20
25
30
ns
tSOP
SEM Flag Update Pulse (OE 10
12
15
20
ns
or SEM)
tSWRD
SEM Flag Write to Read Time 5
10
10
15
ns
tSPS
SEM Flag Contention
5
10
10
15
ns
Window
tSAA
SEM Address Access Time
15
25
35
55
ns
Data Retention Mode
Timing
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5V).
VCC
CE
Parameter
ICCDR1
Notes:
19. Test conditions used are Load 2.
20. tBDD is a calculated parameter and is the greater of tWDD– tPWE (actual) or tDDD– tSD (actual).
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Data Retention Mode
4.5V VCC > 2.0V 4.5V
VCC to VCC – 0.2V
Test Conditions[21]
@ VCCDR = 2V
tRC
VIH
Max.
1.5
Unit
mA
Document #: 38-06035 Rev. *C
Page 10 of 21
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