CY7C0241V Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C0241V

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms

Read Cycle No.1 (Either Port Address Access)[22, 23, 24]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No.2 (Either Port CE/OE Access)[22, 25, 26]

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[22, 24, 25, 26]

tRC

ADDRESS

tAA

UB or LB

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

CY7C024V/025V/026V

CY7C0241V/0251V/036V

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

tHZCE

Notes:

22. R/W is HIGH for read cycles.

23. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

24. OE = VIL.

25. Address valid prior to or coincident with CE transition LOW.

26. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

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