CY7C026A-20AC(2000) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C026A-20AC Datasheet PDF : 17 Pages
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CY7C026A
CY7C036A
Architecture
The CY7C026A and CY7C036A consist of an array of 16K
words of 16 and 18 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These con-
trol pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to
the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be utilized for port-to-port communica-
tion. Two Semaphore (SEM) control pins are used for allocat-
ing shared resources. With the M/S pin, the devices can func-
tion as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The devices also have an automatic power-
down feature controlled by CE. Each port is provided with its
own Output Enable control (OE), which allows data to be read
from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 wave-
form) or the CE pin (see Write Cycle No. 2 waveform). Re-
quired inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox
for the right port and the second-highest memory location
(3FFE) is the mailbox for the left port. When one port writes to
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C026A and CY7C036A provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs
within tPS of each other, the busy logic will determine which
port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a con-
tention situation. When tied HIGH, the M/S pin allows the de-
vice to be used as a master and, therefore, the BUSY line is
an output. BUSY can then be used to send the arbitration out-
come to a slave.
Semaphore Operation
The CY7C026A and CY7C036A provide eight semaphore
latches, which are separate from the dual-port memory loca-
tions. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the sema-
phore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same man-
ner as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes con-
trol by writing a one to the semaphore, the semaphore will be
set to one for both sides. However, if the right port had request-
ed the semaphore (written a zero) while the left port had con-
trol, the right port would immediately own the semaphore as
soon as the left port released it. Table 3 shows sample sema-
phore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to ac-
cess the semaphore within tSPS of each other, the semaphore
will definitely be obtained by one side or the other, but there is
no guarantee which side will control the semaphore.
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