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CY7C027V-15AXI

3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM

Cypress Semiconductor 

CY7C027V/027AV/028V

CY7C037AV/038V

AC Test Loads and Waveforms

3.3 V

Figure 3. AC Test Loads and Waveforms

OUTPUT

C = 30 pF

R1 = 590 

R2 = 435 

OUTPUT

RTH = 250 

C = 30 pF

OUTPUT

VTH = 1.4 V

C = 5 pF

3.3 V

R1 = 590 

R2 = 435 

(a) Normal Load (Load 1)

(b) Thévenin Equivalent (Load 1)

ALL INPUT PULSES

(c) Three-State Delay (Load 2)

(Used for tLZ, tHZ, tHZWE, & tLZWE

including scope and jig)

3.0V

GND

10%

 3 ns

90%

90%

10%

 3 ns

Data Retention Mode

The CY7C027V/027AV/028V and CY7037AV/038V are de-

signed with battery backup in mind. Data retention voltage and

supply current are guaranteed over temperature. The following

rules ensure data retention:

1. Chip Enable (CE) must be held HIGH during data retention, within

VCC to VCC – 0.2 V

2. CE must be kept between VCC – 0.2 V and 70% of VCC during

the power up and power down transitions

3. The RAM can begin operation >tRC after VCC reaches the

minimum operating voltage (3.0 V)

Timing

VCC

CE

Data Retention Mode

3.0 V VCC 2.0 V 3.0 V

VCC to VCC – 0.2 V

tRC

VIH

Parameter

ICCDR1

Test Conditions [12]

At VCCDR = 2 V

Max Unit

50

A

Note

12. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.

Document Number: 38-06078 Rev. *G

Page 8 of 24

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