CY7C1021D(2009) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1021D
(Rev.:2009)

1-Mbit (64K x 16) Static RAM

Cypress Semiconductor 

CY7C1021D

Switching Waveforms (continued)

Figure 5. Write Cycle No. 1 (CE Controlled) [16, 17]

tWC

ADDRESS

CE

WE

BHE, BLE

DATA I/O

tSA

tSCE

tAW

tHA

tPWE

tBW

tSD

tHD

ADDRESS

BHE, BLE

WE

CE

DATA I/O

Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)

tWC

tSA

tBW

tAW

tHA

tPWE

tSCE

tSD

tHD

Notes

16. Data I/O is high impedance if OE or BHE and/or BLE = VIH.

17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

Document #: 38-05462 Rev. *F

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